1. Field of the Invention
The present invention relates to a semiconductor device having a power cutoff function.
2. Description of the Related Art
A power short-circuit examination for detecting a power short-circuit defect, as one of defective modes of a semiconductor device (Large Scale Integration: LSI) is generally embodied in the examination processing of the semiconductor device.
FIGS. 26A and 26B show the power short-circuit examination of the semiconductor device. In the power short-circuit examination of a semiconductor device IC1 shown in FIG. 26A, voltages applied to power terminals Pvdd1, Pvdd2, and Pvdd3, and a ground terminal Pvss are set as shown in FIG. 26B and current thereof is measured. Further, the result of measurement is compared with a predetermined value, thereby selecting the semiconductor device IC1. More specifically, in a state for applying 0V to the power terminals Pvdd2 and Pvdd3 and the ground terminal Pvss, a minute voltage by which a circuit block BK1 does not operate is applied to the power terminal Pvdd1 and current thereof is measured. When the result of measurement is over the predetermined value, a power short-circuit (A) between a power line VDD1 and a ground line VSS and a power short-circuit (B) between the power line VDD1 and a power line VDD2 are detected. Then, the semiconductor device IC1 is selected as a defective product having the power short-circuit as a power short defect. In a state in which a voltage 0V is applied to the power terminals Pvdd1 and Pvdd3 and the ground terminal Pvss, a minute voltage by which a circuit block BK2 does not operate is applied to the power terminal Pvdd2 and current thereof is measured. When the result of measurement is over a predetermined value, a power short-circuit (B) between the power line VDD1 and the power line VDD2 and a power short-circuit (C) between the power line VDD2 and a power line VDD3 are detected, and the semiconductor device IC1 is selected as a defective product having a power short-circuit. In a state in which a voltage 0V is applied to the power terminals Pvdd1 and Pvdd2 and the ground terminal Pvss, a minute voltage by which a circuit block BK3 does not operate is applied to the power terminal Pvdd3 and current thereof is measured. When the result of measurement is over a predetermined value, the power short-circuit (C) between the power line VDD2 and the power line VDD3 and a power short-circuit (D) between the power line VDD3 and the ground line VSS are detected, and the semiconductor device IC1 is selected as a defective product having a power short-circuit.
The power short-circuit examination is an important examination not only to select the defective product having the power short-circuit but also to protect an external examination environment of an examination device. Although a power short-circuit of 10 mΩ exists between the power line and the ground line within the semiconductor device, if a rated voltage of 1.5V is applied to the power terminal of the semiconductor device, extremely large current of 150 A flows and the external examination environment can be thus destroyed. Therefore, the power short-circuit examination is usually embodied in the initial stage of the examination processing.
Recently, for portable electrical apparatuses, such as a mobile phone and a digital camera, low-power consumption of the semiconductor device mounted on the electrical apparatus is strongly requested, and a semiconductor device having a power-cutoff function is increasingly used. For the purpose of reduction in power consumption of the semiconductor device, the power cutoff function cuts-off the supply of a power-supply voltage depending on the use for every circuit block in the semiconductor device. Although the installation of the power cutoff function to the semiconductor device is effective for reducing the power consumption, this causes a problem in the power short-circuit examination.
FIGS. 27A and 27B shows a problem upon installing the power cutoff function to the semiconductor device. A description will be given of the problem upon installing the power cutoff function to the semiconductor device with a semiconductor device IC2 shown in FIG. 27A as an example. The semiconductor device IC2 comprises circuit blocks BK1 and BK2 and power cutoff switches SW1 and SW2 for embodying the power cutoff function. The power cutoff switch (pMOS transistor) SW1 is connected between a power line VDD1 and a power line VDDM1 dedicated for the circuit block BK1, is turned on when the circuit block BK1 is used, and is turned off when the circuit block BK1 is not used. The power cutoff switch (pMOS transistor) SW2 is connected between a power line VDD2 and a power line VDDM2 dedicated for the circuit block BK2, is turned on when the circuit block BK2 is used, and is turned off when the circuit block BK2 is not used. With the semiconductor device IC2 having the above structure, in a state in which the power cutoff switches SW1 and SW2 are turned off, the power short-circuit examination can be embodied. Therefore, the power short-circuit examination cannot detect a part of the power short-circuits. Referring to FIG. 27B, a minute voltage is applied to a power terminal Pvdd1 and current thereof is measured in a state in which a voltage 0V is applied to a power terminal Pvdd2 and a ground terminal Pvss. The result of measurement is compared with a predetermined value, thereby detecting a power short-circuit (A) between a power line VDD1 and a power line VDD2. However, when the power cutoff switches SW1 and SW2 are turned off, it is not possible to detect a power short-circuit (C) between the power line VDD1 and the power line VDDM1, a power short-circuit (D) between the power line VDDM1 and the ground lines VSS, and a power short-circuit (E) between the power line VDDM1 and the power line VDDM2. Further, in a state in which a voltage 0V is applied to the power terminal Pvdd1 and the ground terminal Pvss, a minute voltage is applied to the power terminal Pvdd2 and current thereof is measured. The result of measurement is compared with a predetermined value, thereby detecting the power short-circuit (A) between the power line VDD1 and the power line VDD2 and the power short-circuit (B) between the power line VDD2 and the ground line VSS. However, when the power cutoff switches SW1 and SW2 are turned off, it is not possible to detect the power short-circuit (E) between the power line VDDM1 and the power line VDDM2. As mentioned above, in the semiconductor device IC2 having the above structure, the power short-circuits (C), (D), and (E) cannot be detected by the power short-circuit examination. Although the power short-circuit (D) exists in the semiconductor device IC2, if it is determined that the semiconductor device IC2 is a non-defective product, the power cutoff switch SW1 is turned on when a rated voltage is applied to the power terminal Pvdd1 in an examination different form the power short-circuit examination, thereby destroying the external examination environment.
As a conventional art for solving the problem, such a method is known that a pad for examination connected to a power line dedicated for a circuit block is provided, a minute voltage is applied to the pad for examination in addition to a power terminal in the power short-circuit examination and current thereof is measured.
FIGS. 28A and 28B show a power short-circuit examination of a semiconductor device having a power cutoff function. A semiconductor device IC3 shown in FIG. 28A is structured by adding pads PD1 and PD2 for examination to the semiconductor device IC2 shown in FIG. 27A. In a power short-circuit examination of the semiconductor device IC3 having the power cutoff function, voltages applied to the power terminals Pvdd1 and Pvdd2, the pad PD1 and PD2 for an examination, and the ground terminal Pvss are set as shown in FIG. 28B and current thereof is measured. The result of measurement is compared with a predetermined value, thereby selecting the semiconductor device IC3. More specifically, in a state for applying a voltage 0V to the power terminal Pvdd2, the pads PD1 and PD2 for examination, and the ground terminal Pvss, a minute voltage is applied to the power terminal Pvdd1 and current thereof is measured. When the result of measurement is over the predetermined value, the power short-circuits (A) and (C) are detected, and the semiconductor device IC3 is selected as a defective product having the power short-circuit. Further, in a state for applying a voltage 0V to the power terminal Pvdd1, the pads PD1 and PD2 for examination, and the ground terminal Pvss, a minute voltage is applied to the power terminal Pvdd2 and current thereof is measured. When the result of measurement is over a predetermined value, the power short-circuits (A) and (B) are detected and the semiconductor device IC3 is selected as a defective product having the power short-circuit. Furthermore, in a state for applying a voltage 0V to the power terminals Pvdd1 and Pvdd2, the pad PD2 for examination, and the ground terminal Pvss, a minute voltage is applied to the pad PD1 for examination and current thereof is measured. When the result of measurement is over a predetermined value, the power short-circuits (C), (D), and (E) are detected and the semiconductor device IC3 is selected as a defective product having the power short-circuit. In addition, in a state for applying a voltage 0V to the power terminals Pvdd1 and Pvdd2, the pad PD1 for examination, and the ground terminal Pvss, a minute voltage is applied to the pad PD2 for examination and current thereof is measured. When the result of measurement is over a predetermined value, the power short-circuit (E) is detected and the semiconductor device IC3 is selected as a defective product having the power short-circuit. The pads PD1 and PD2 for examination connected to the power lines VDDM1 and VDDM2 are arranged as mentioned above, thereby detecting all the power short-circuits (A) to (E) even if the power cutoff switches SW1 and SW2 are turned off in the power short-circuit examination.
In Japanese Laid-open Patent Publication No. 3-36748 and Japanese Laid-open Patent Publication No. 8-201474, disclosed is a technology that the pad for examination is disposed in the semiconductor device, a voltage is applied to the pad for examination, and current thereof is measured, or current is applied and a voltage thereof is measured so as to specify a defective portion in the semiconductor device.
If the power cutoff function is not controlled finely depending on the circuit blocks in the semiconductor device having the power cutoff function, the advantage for reducing the power consumption is small, and the number of internal power lines dedicated for circuit block exceeds 10 in some cases. Therefore, it is necessary to provide a large number of pads for examination in the semiconductor device according to the conventional art. Since the size of the pad for examination is prescribed by the specification of the examination device, even if the manufacturing technology of the semiconductor device advances and the circuit integration improves, the size of the pad for examination is not small. Therefore, the chip size of the semiconductor device cannot be small, and the manufacturing cost of the semiconductor device increases.